The present invention relates to a single-end-zero receiver circuit for differential data.
A conventional single-end-zero receiver circuit for differential data will be described with reference to FIGS. 1 and 2.
FIG. 1 shows an example of conventional single-end-zero receiver circuits. FIG. 1 shows a DATA+ input terminal 101, a DATAxe2x88x92 input terminal 102, Schmitt buffers 103 and 104, a NOR gate circuit 105, and an SE0 output terminal 106. The DATA+ input terminal 101 inputs a differential data input signal DATA+. And the DATAxe2x88x92 input terminal 102 input a differential data input signal DATAxe2x88x92. The two input terminals connect to the NOR gate circuit 105 through each of the Schmitt buffers 103 and 104 respectively. The outputs of the NOR gate circuit 105 is connects to the SE0 output terminal 106.
FIG. 2 is a timing chart on the single-end-zero receiver circuit of FIG. 1. FIG. 2 shows a differential data input signal DATA+ of the DATA+ input terminal 101, a differential data input signal DATAxe2x88x92 of the DATAxe2x88x92 input terminal 102, respective outputs of the Schmitt buffers 103 and 104, and a single-end-zero signal SE0 to be output from the SE0 output terminal 106.
Each of the Schmitt buffers 103 and 104 shown in FIG. 1 has input threshold hysteresis. Therefore, as shown in FIG. 2, the output of the Schmitt buffer 103 varies in order at timing points a1, a4, a5, and a6 with timing deviations that are based on input threshold values. Similarly, the output of the Schmitt buffer 104 varies in order at timing points a2 and a3. The single-end-zero signal SE0 is obtained by decoding the outputs of the Schmitt buffers 103 and 104 with the NOR gate circuit 105. Therefore, glitches g1 and g2 occur on the SE0 output terminal in the period between the timing points al and a2 and the period between the timing points a3 and a4, respectively.
However, the active period of the single-end-zero signal SE0 that is actually necessary is the period between the timing points a5 and a6. And the glitches g1 and g2 occur on the SE0 output terminal 106 when the differential data input signals DATA+ and DATAxe2x88x92 cross each other, as described above.
Accordingly, a certain measure against glitches needs to be taken on the input side of the single-end-zero signal SE0, which means a limitation on circuit designing.
An object of the present invention is to provide a single-end-zero receiver of differential data which prevents an erroneous operation of the internal circuits due to glitches and dispenses with any circuit as a countermeasure against glitches.
The invention provides a single-end-zero receiver circuit comprising a low-value threshold detector, a high-value threshold detector, and a set/reset latch circuit.
The low-value threshold detector receives both of first and second differential data input signals and for detecting whether both of the first and second differential data input signals are lower than a first threshold voltage. The high-value threshold detector receives both of the first and second differential data input signals and for detecting whether one of the first and second differential data input signals is higher than a second threshold voltage that is higher than the first threshold voltage.
And the set/reset latch circuit outputs an SE0 signal.
The set/reset latch circuit is set when levels of both of the first and second differential data input signals are lower than or equal to the first threshold voltage. And the set/reset latch circuit is reset when one of the levels of the first and second differential data input signals is higher than or equal to the second threshold voltage.
Each of the above components can easily be structured as a logic circuit. Since glitches are prevented from occurring on the SE0 output terminal or in a single-end-zero signal when two differential data input signals cross each other, no glitch-induced erroneous operation occurs in the internal circuits. Further, no external circuit as a countermeasure against glitches is necessary.